`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: University of Utah	
// Engineer: David Hurst, Tyson Hunt, Chase Hochstrasser
//
// Create Date:   13:18:34 09/15/2011
// Design Name:   Regfile
// Module Name:   C:/Users/david/16bitcpu/Regfile_test.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Regfile
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Regfile_test;

	// Inputs, Registers
	reg CLK;
	reg reset;
	reg [3:0] rd_address1;
	reg [3:0] rd_address2;
	reg wr_en;
	reg [3:0] write_address;
	reg [15:0] write_data;

	// Outputs
	wire [15:0] read_data1;
	wire [15:0] read_data2;

	// Instantiate the Unit Under Test (UUT)
	Regfile uut (
		.CLK(CLK), 
		.reset(reset), 
		.rd_address1(rd_address1), 
		.rd_address2(rd_address2), 
		.read_data1(read_data1), 
		.read_data2(read_data2), 
		.wr_en(wr_en), 
		.write_address(write_address), 
		.write_data(write_data)
	);

	initial begin
		// Initialize Inputs
		CLK = 0;
		reset = 0;
		rd_address1 = 0;
		rd_address2 = 0;
		wr_en = 0;
		write_address = 0;
		write_data = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

		// Write
		wr_en = 1;
		write_data = 42;
		write_address = 15;
		
		#10; // Wait 10 ns
		
		wr_en = 1;
		write_data = 2;
		write_address = 1;
		
		#10;

		wr_en = 0;
		rd_address1 = 15;


		#10
		
		rd_address1 = 2;
		// Check for Register Failure
		if (read_data1 != 42)
			$display("Register Failure!");
		end
		
		// Always block
		always begin
			#5; // Wait 5 ns
			CLK = ~CLK; // Clcok inverted
		end
		
// Stop, Do Not Pass GO, Do Not Collect 200 Dollars
endmodule

